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Training program AE

AE620. Hardware Programing: FPGA and ASIC design

This training is targeted for digital design techniques for beginners and advance designers. The course is divided into three parts as explained

Digital Design Techniques and Methodology-I: Beginners

Intended Trainee

New graduate engineers embarking on a first project, or engineers w limited practical New graduate experience of digital design

Engeers from other disciplines (eg software design or analog design) re-training for digttal design involvement, or requ g fam arization with modern d al design techniques

Knowledge Acquired

Combinational and Sequential Logic Design for PLDs and ASICs, with an emphasis on synchronous design techniques

How to design and implementfundamental structures e.g. decoders, multiplexers, shift registers Counters

How to design and implement synchronous Finite State Machines

An overview of ASIC and field programmable logic design including a survey ofstate of the art devices

Designing with programmable devices

Effective Design methodologies and flows


Introduction Designing with programmable logicandASICs #Synchronous design techniques #Using HDLs

Digital Design Fundamentals Representing bits and three-states Unsigned and signed (two's complement) numbers #Static and dmamic definition of combinational logic Logic minimization #Avoiding asynchronous sequential logic

Synchronous Sequential Logic Principles #Using D-type flip-flops Characterization-timing constraints #Timing violations and metaStability issues #Timing performance of synchronous systems #Static timing analysis #.ther flip-flop types

An Overview of HDL-Based Design First and second generation HDLs#vHDLandVerilog+Design process usingHDLS

Introduction to Programmable Logic Survey of programmable logic devices Selecting an appropriate device #Importance of the internal structure ม.pin Standards Pull-ups, open collector, triStates and bi-directional tristate bubble-up Pinassignment#ITAG boundary Scan

Common Functions and ther Implementation Encoders and decoders Priority encoders #Multiplexers #Tristates used as Muxes #Parity generator #Shift Registers #Johnson (ring) "counters" #Linear Feedback Shit Registers

Anthmet1c Smctures o Half and full adders Large adders #Carry lookahead adder# Pipelining #Smthesis of adders Counters Wide counters #Binary to BCD conversion Serial arithmetic Importance of Synchronous design

Synchronous Finite State Machines and Memories o Definition# Graphical entry and symbolism #Moore and Mealy structures #Implementation State encoding and optimization Using HDLS to design FSMS Using memories #Memory types

SIntroduction to ASICs - ASIC types and technologies #ASIC economics *Design for test# Design process for ASICs

Estimated Training Period:

4 Days

Required Software:

Mentor Modelsim