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Training program AE

AE640; Digital Design Techniques and Methodology-III: Advanced VHDL
Intended Trainee

Engineers who have already acquired some practical experience in the use of VHDL, but wish to consolidate and extend their knowledge within a training environment

Engineers who are about to embark on the VHDL H ardware design project

Knowledge acquired

The VHDL language concepts constructs essential for complex FPGA and ASIC design

The VHDL language constructs and coding styles that enable sophisticated test benches

How to code hierarchical designs using multiple VHDL design libraries

How to write re-usable, parameterisable VHDL code by exploiting generics anddata types

How to run gate-level simulations


More About Types Variables g Loops Std logic and resolution #Array and integer subtypes #Aggregates

Managing Hierarchical Designs Fierarchical design flow & Library name mapping 4 Component declaration A Configuration Hierarchical configurations MCompilation order

Parameterised Design Entities Amay and type attributes# Port Maps # Generics and Generic Maps # Generate statement # Generics and generate

Procedural Testbenches Subprograms Procedures #Functions #Parameters and Parameter Association #Package declarations #Package bodies# Subprograms in packages # subprogram overloading # Operator overloading # Qualified expressions #RTL Procedures

Text-File-Based Testbenches Assertions #Opening and closing files # Catching TEXTIO errors #Convertingbetween VHDL types and strings# Checking simulation results# Initialising memories # Foreign bodies

Gate Level Simulation Rationale for gate level simulation# VITAL tool flow #Reuse of RTL testbench at gate level # Comparison ofRTLand gate level results d Behavioral modelling

Estimated Training Period:

4 Days

Required Software/Hardware:

Mentor Modelsim

ALTERA DE-2 115 board DE2 NANO board