Training program DD
DD 5108 Digital Design Techniques and Methodology -I: Beginners
Intended Trainee
New graduate engineers embarking on a first project or engineers with limited practical
experience of digital design Engineers from other disciplines (e.g. software design or analog design) re-training for digital design involvement, or requiring familiarization with modern digital design techniques.
Knowledge Acquired
Combinational and Sequential Logic Design for PLDs and ASICs, with an emphasis on synchronous design techniques
How to design and implement fundamental structures e. g. decoders, multiplexers, shift registers, counters
How to design and implement synchronous Finite State Machines
An overview of ASIC and field programmable logic design including a survey ofstate of the art devices
Designing with programmable devices
Effective Design methodologies and flows
Content
Designing with programmable logic and ASICs #Synchronous design techniques #Using HDLs
Representing bits and three-states # Unsigned and signed (two's complement) numbers #Static and dynamic definition ofcombinational #logic ta Logic minimization Avoiding asynchronous sequential logic
Principles #Using D-type flip-flops #Characterization timing constraints #Timing violations and metastability issues #Timing performance of synchronous systems #Static timing analysis #Other flip-flop types
First and second generation HDLs HVHDL and Verilog, #Design process using HDLs
Survey of programmable logic devices #Selecting an appropriate device Importance of the intemal structure #I/O pin standards # Pull-ups; open collector tristates and bi-directional tristate bubble-up #Pin assignment #JTAG boundary scan
Encoders and decoders Priority encoders #Multiplexers #Tristates used as Maxes #Parity generator #Shift Registers H Johnson (ring) "counters" #Linear Feedback shift Registers
Halfand full adders #Large adders #Carry look ahead adder & Pipelining #Synthesis of adders #Counters #Wide counters # Binary to BCD conversion #Serial arithmetic #Importance of synchronous design
Definition # Graphical entry and symbolism #Moore and Mealy structures #Implementation # State encodingand optimization #Using HDLs to design FSMs #Using memories f Memory types
ASIC types and technologies #ASIC economics #Design for test #Design process for ASICs
Estimated Training Period:
2 Days
Required Software:
Mentor Modelsim
