Training program AE
AE 630 Digital Design Techniques and Methodology-II: VHDL for FPGA Design
Intended Trainee
Engineers who wish to becomeskilled in the practical use of VHDL for FPGA or ASIC design
Engineers who are about to embark on the first VHDL design project
Knowledge acquired
VHDL language concepts and constructs essential for FPGA design
How to write VHDL for effective RTL synthesis
How to target VHDL code to an FPGA device architecture
How to write simple VHDL test benches
The tool flow from VHDL through simulation, synthesis and place-and-route
Content
Introduction The scope and application of VHDL H Design and tool flow FPGAs #TheWDL world
Getting started The basic VHDL language constructs VHDL, source files and libraries The compilation procedure #Synchronous design and timing constraints
FPGA Design Flow (Practical exercises using a hardware board) Simulation #Smbesis Place-and-Route A Device programming
Design Entities Entities and Architectures #Std logic #Signals and ports, # Concurrent assignments # Instantiation and Port Maps The Context Clause
Processes The Process statement th sensitivity list versus Wait# signal assignments and delta delays # Register transfers# Default assignment # Simple Testbenches
Synthesizing Combinational Logic If statements # Conditional signal assignments and Equivalent process # Transparent latches # Case statements #Synthesis of combinational logic
Types VHDL types le standard packages # Integer subtypes# std logic and std logic_vector Slices and concatenation #Integer and vector values
Synthesis of Arithmetic Arithmetic operator overloading #Arithmetic packages # Mixing integers and vectors # Resizing vectors# Resource sharing
Synthesising sequential Logic RISING_EDGE #Asynchronous set or reset # Synchronous inputs and clock ena Synthesisable process templates #Implying registers
FSM Synthesis Enumeration types #VHDL coding styles for FSMs #state encoding #Umeachable states and input hazards
Memories Amay types # Modelling memories #IP Generators #Instantiating generated components # ImplementingROMs
Basic TEXTIO TEXTIO# READ and WRITE # Using TEXTIO for testbench stimulus and outputs # STD LOGIC_TEXTIO
Estimated Training Period:
4 Days
Required Software/Hardware:
Mentor Modelsim
ALTERA DE-2 115 board/DE2 NANO Board
