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Training program DD


DD 520: Digital Design Techniques and Methodology -II: VHDL for FPGA Design(I), Introductory level
Intended Trainee

Engineers who wish to become skilled in the practical use of VHDL for FPGA or ASIC design

Engineers who are about to embark on the frst VHDL design project


Knowledge Acquired

VHDLlanguage concepts and constructs essential for FPGA design

How to write VHDL for effective RTL synthesis

How to target VHDL code to an FPGA devicearchitecture

How to write simple VHDL test benches

The tool flow from VHDL through simulation, synthesis and place-and route


Content
Introduction

The scope and application ofVHDL #Design and tool fow #FPGAs #The VHDL world

Getting Started

The basic VHDLlanguage constructs #VHDL source files and librarie #The compilation procedure #Synchronous design and timing constraints

FPGA Design Flow (Practical exercises using a hardware board)

Simulation #Synthesis #Place-and-Route #Device programming

Design Entities

Entities and Architectures #Std logic #Signals and Ports #Concurrent assignments #Instantiation and Port Maps #The Context Clause

Processes

The Process statement #Sensitivity list versus Wait #Signal assignments and delta delays #Register transfers #Default assignment #Simple Test benches

Synthesizing Combinational Logic

lf statements #Conditional signal assignments and Equivalent process #Transparent latches # Case statements Synthesis of combinational logic


Estimated Training Period:

2 Days


Required Software:

Mentor Modelsim