Engineers who wish to become skilled in the practical use of VHDL for FPGA or ASIC design
Engineers who are about to embark on the frst VHDL design project
VHDLlanguage concepts and constructs essential for FPGA design
How to write VHDL for effective RTL synthesis
How to target VHDL code to an FPGA devicearchitecture
How to write simple VHDL test benches
The tool flow from VHDL through simulation, synthesis and place-and route
The scope and application ofVHDL #Design and tool fow #FPGAs #The VHDL world
The basic VHDLlanguage constructs #VHDL source files and librarie #The compilation procedure #Synchronous design and timing constraints
Simulation #Synthesis #Place-and-Route #Device programming
Entities and Architectures #Std logic #Signals and Ports #Concurrent assignments #Instantiation and Port Maps #The Context Clause
The Process statement #Sensitivity list versus Wait #Signal assignments and delta delays #Register transfers #Default assignment #Simple Test benches
lf statements #Conditional signal assignments and Equivalent process #Transparent latches # Case statements Synthesis of combinational logic
2 Days
Mentor Modelsim