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Training program DD

DD 530: Digital Design Techniques and Methodology-III: VHDL for FPGA Design(II), Intermediate level
Intended Trainee

Engineers who wish to become skilled in the practical use of VHDL for FPGA or ASIC design

Engineers who are about to embark on the first VHDL desigi project

Knowledge Acquired

VHDL language concepts and constructs essential for FPGA design

How to wite VHDL for effective RTL synthesis

How to target VHDL code to an FPGA device architecture

How to wite simple VHDL test benches

The tool flow from VHDL through simulation, synthesis and place-and-route


VHDL types Standard packages #Integer subtypes# std_logic and std_logic_vector #Slices and concatenation Integer and vector values

Synthesis of Arithmetic

Anthmetic operator overloading # Artimetic packages # Mixing integers and vectors # Rizing vectors # Resource sharing

Synthesizing Sequential Logic

RISING_EDGE #Asynchronous set or reset #Synchronous inputs and clock enables #Synthesizable process templates #implying registers

FSM Synthesis

Enumeration types #VHDL coding styles for FSMs #State encoding #Unreachable states and input hazards


Array types #Modelling memories #IP Generators #Instantiating generated components #lmplementing ROMs


TEXTIO # READ and WRITE #Using TEXTIO for test bench stimulus and outputs #STD LOGIC TEXTIO

Estimated Training Period:

5 Days

Required Software:

Mentor Modelsim