Engineers who wish to become skilled in the practical use of VHDL for FPGA or ASIC design
Engineers who are about to embark on the first VHDL desigi project
VHDL language concepts and constructs essential for FPGA design
How to wite VHDL for effective RTL synthesis
How to target VHDL code to an FPGA device architecture
How to wite simple VHDL test benches
The tool flow from VHDL through simulation, synthesis and place-and-route
VHDL types Standard packages #Integer subtypes# std_logic and std_logic_vector #Slices and concatenation Integer and vector values
Anthmetic operator overloading # Artimetic packages # Mixing integers and vectors # Rizing vectors # Resource sharing
RISING_EDGE #Asynchronous set or reset #Synchronous inputs and clock enables #Synthesizable process templates #implying registers
Enumeration types #VHDL coding styles for FSMs #State encoding #Unreachable states and input hazards
Array types #Modelling memories #IP Generators #Instantiating generated components #lmplementing ROMs
TEXTIO # READ and WRITE #Using TEXTIO for test bench stimulus and outputs #STD LOGIC TEXTIO
5 Days
Mentor Modelsim