Training program DD
540: Digital Design Techniques and Methodology IV: VHDL for FPGA מס Design(III) Advanced Level
Intended Trainee
Engineers who have already acquired some practical experience in the use of VHDL, but wish to consolidate and extend their knowledge within a training environment
Engineers who are about to embark on the VHDL/Hardware design project
Knowledge Acquired
The VHDL language concepts constructs essential for complex FPGA and ASIC design
The VHDL language constructs and coding styles that enable sophisticated test benches
How to code hierarchical designs using multiple VHDLdesign libraries How to write re-usable, parameterisable VHDL code by exploiting generics and data types
How to run gate-level simulations
Content
Variables #Loops #Std logic and resolution #Array and integer subtypes #Aggregates
Hierarchical design flow #Lbrary name mapping #Component declaration #Configuration a Hierarchical configurations #Compilation order
Array and type attributes #Port Maps #Generics and Generic Maps #Generate statement #Generics and generate
Subprograms #Procedures #Functions #Parameters and Parameter Association #Package declarations #Package bodies #subprograms inpackages#Subprogram overloading # Operator overloading # Qualified expressions H RTL Procedures
Assertions #Opening andclosing fles #Catching TEXTI errors # Converting between VHDL types and strings #Checking simulation results #Initializing memores #Foreign bodies
Rationale for gate level simulation #VITAL tool flow #Reuse ofRTL test bench at gate level #Comparison ofRTL and gate level results fr Behavioral modelling
Estimated Training Period:
2 Days
Required Software:
Mentor Modelsim
